display / touch / bonding solutions
A serialiser and deserialiser pair solves a problem that ordinary parallel and low-voltage links cannot: it carries an enormous pixel rate across a cable that has to survive a vehicle, a machine or a building. What it does not do is make the electrical design easy. The channel, the clocking, the power and the thermal path all become first-order concerns, and the display is no longer the most demanding part of the system.
Pixels, control and often power in one pair.
A SerDes link serialises the display data, the control channel and frequently the power on one or two conductors, so a display can sit metres from the host with a cable that is thin, flexible and cheap.
That combination is why the architecture appears in vehicles, industrial machines and medical carts, where the panel is remote from the electronics and the harness has to survive movement and vibration. The serialiser sits near the host, the deserialiser near the panel, and the link between them carries a forward channel for video and a back channel for control and diagnostics. Because the control channel is bidirectional and low speed, the same cable can carry touch data, backlight control, a temperature reading and a fault log, which removes the separate harness that a parallel interface would need. The trade is that the link is now a high-speed analogue system, and the display design inherits its constraints.
Controlled impedance, bandwidth and a return path.
As the data rate rises, the cable stops behaving as a wire and starts behaving as a transmission line, so impedance control, insertion loss and the return path decide whether the link closes.
Three requirements tighten together. The impedance of the cable, the connector and the board trace has to match within a tolerance that holds across the frequency range, because a mismatch produces reflections that close the eye at the receiver. The insertion loss has to stay inside the equaliser budget, which limits the practical cable length and the number of connectors in the path. And the return path has to be continuous, because at these rates the return current follows the signal path and a broken reference plane produces radiated noise and a link that works on one sample and not the next. The physical-layer rules for the mobile-style links are defined by the MIPI DSI specification and the MIPI CSI-2 specification, while an automotive serialiser family such as TI FPD-Link documents the channel expectations for its own devices.
The clock is embedded and recovered.
Most display SerDes links embed the clock in the data stream and recover it at the deserialiser, so there is no separate clock conductor and the timing budget moves into the recovered clock's jitter.
That is convenient for the harness and demanding for the design. Because the clock is recovered, any jitter on the link becomes jitter on the recovered clock, and the panel's timing controller has to tolerate it. The practical controls are to keep the trace between the deserialiser and the panel as short as possible, to hold the reference clock quality at the serialiser, and to avoid routing the link alongside switching supplies or backlight drivers whose noise would be added to the stream. Where the panel sits on the same board as the deserialiser, the connection can be made with a conventional low-voltage link, which is the pattern used in several display modules.
Five entries carry the risk.
The entries that decide whether the link works are the required pixel rate, the cable type and length, the connector count, the equaliser and power budget at the deserialiser, and the thermal path at both ends.
| Entry | SerDes link | Parallel or LVDS harness |
|---|---|---|
| Conductors | One or two pairs | Ten or more |
| Cable length | Metres, within the equaliser budget | Under a metre for LVDS, short for parallel |
| Control channel | Bidirectional on the same cable | Separate wires |
| Channel design | Impedance, loss and return path are critical | Termination and skew dominate |
| Diagnostics | Link status and fault logs available | Little visibility |
The diagnostics row is an advantage that is often overlooked in design reviews, because a link that reports its own error counters makes an intermittent fault measurable rather than anecdotal. The safety context for the finished equipment follows IEC 62368-1 where it applies, and the workmanship expectations for the assemblies at both ends follow IPC practice.
The link becomes a qualified subsystem.
When the display is connected by a SerDes link, the panel, the serialiser, the deserialiser, the cable and the connectors form one qualified subsystem, so a substitution anywhere in that chain requires the link to be re-verified.
That changes the commercial conversation in three ways. The specification sent to a supplier has to state the link, the cable type and the length, because the panel behaviour depends on the recovered clock quality. The evidence offered should include the link margin or error counts at the extremes of temperature and cable length, not only the panel's optical data. And availability has to be considered across the whole chain, since a deserialiser reaching end of life is as disruptive as a panel reaching end of life, and the second-source qualification covers both. Panel and product-life movements for the display side are tracked commercially by research houses such as TrendForce.
Four readings mislead.
The first is treating a working bench link as proof that the production harness will work, when the bench cable is short and the production cable is not. The second is assuming the link budget is a property of the chip alone, when the cable and connectors consume most of it. The third is ignoring the thermal path at the deserialiser, which sits near the panel and often in the warmest part of the enclosure. The fourth is overlooking the control channel's value during field diagnosis.
Each misreading has a cheap corrective. Test the link over the production cable length and routing before the design freezes, and record the error counters rather than only the image. Ask the component vendor for the channel requirements and compare them with the cable data rather than with a rule of thumb. Place the deserialiser with the thermal path in mind, since its power dissipation joins the backlight's inside a sealed enclosure. And enable the diagnostics early, because a link that reports its own margin is far easier to qualify than one that only shows an image.
Link margin at the worst cable and temperature.
Before freezing, measure the link margin or the error count over the production cable at its maximum length, at both temperature extremes, with the production connectors and the production power supplies.
Three supporting checks belong in the review. Confirm the return path and the reference plane through the connectors, because a break at a connector creates an intermittent fault that is difficult to reproduce. Confirm the deserialiser's thermal path against the enclosure model, including the backlight loading. And confirm the firmware handles a link error gracefully rather than presenting a frozen image, since a product that recovers is far easier to support than one that requires a power cycle. The communication between the display and the host over the back channel belongs in the interface documentation, and the physical-layer expectations come from the link's own specification.
The lifecycle covers the whole chain.
A SerDes display has a lifecycle that spans the panel, the serialiser, the deserialiser, the cable and the connectors, and the weakest link in that chain decides how long the product can be built.
The plan should list each element separately and record what happens at end of life for each: the notice period in writing, a last-time-buy quantity tied to the forecast, and a documented alternative that has been evaluated at the link level rather than only at the component level. Where a deserialiser is replaced, the link margin has to be re-measured, because two devices with the same nominal specification can differ in equaliser behaviour. Where the cable changes, the insertion loss has to be compared. A second-source qualification carried out while the first chain is in healthy supply is the control that keeps a linked product buildable, and the recorded margin measurements are what make the substitution cheap.
What is a display SerDes link?
A serialiser and deserialiser pair that carries display data, control and often power over one or two conductor pairs, allowing a panel to sit metres from the host on a thin cable instead of a wide parallel harness.
How far can a display SerDes link run?
It depends on the equaliser budget and the cable, not on a fixed figure. Insertion loss and connector count consume the budget, so the limit is set by the specific cable and the number of connectors in the path rather than by the data rate alone.
Why does a high-speed display link need impedance control?
Because at high data rates the cable behaves as a transmission line. A mismatch between the cable, the connector and the board trace produces reflections that close the eye at the receiver, and the link then fails intermittently rather than cleanly.
Does a SerDes link need its own qualification?
Yes. The panel, the serialiser, the deserialiser, the cable and the connectors behave as one subsystem, so any substitution requires the link margin to be re-measured at the temperature extremes and at the maximum cable length.
Send the pixel rate, the cable type and length, the connector count and the enclosure thermal limit to CDTech; the reply will state which link architecture fits and what margin the channel has to hold.
Contact sales@cdtech-lcd.com or use the contact page to request a specification review, and see the news section for related interface notes.
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